Re: TSC Timecounter and multi-core/SMP

From: Julian Elischer <julian_at_elischer.org>
Date: Fri, 18 Apr 2008 10:54:53 -0700
Poul-Henning Kamp wrote:
> In message <48080276.3040203_at_elischer.org>, Julian Elischer writes:
>> David O'Brien wrote:
>>
>>> The TSC on K8 is not invariant - its rate of change is affected by
>>> P-state changes.
>>>
>>> The TSC on Greyhound (Family 10h) is invariant.
>>> [but as stated above, is not synced with other cores]
>> You'd think that an invariant sync'd clock (fast to read) of some
>> type would have been done by someone by now.. The software people
>> have been asking for this for the last decade at least.
> 
> Actually one of the original design documents for SAGE stressed that
> such hardware were crucially important "for any system operating
> in real time", so yes, the HW people have had adequate notices.
> 
> Poul-Henning
> 
> 

I'm certain that earlier systems had it as a requirement but I wasn't
willing to lump the IBM 407 or 1620  in to the same bucket as an SMP
PC with the ability to change the frequency on each CPU. I remember
that the MP vaxen and PDPs had good timers.. and I'm certain the MP
IBMs did too.

How hard can it be?

An instruction that gives a 64 bit counter, in some reasonable
granularity that is run at the same speed for all CPUS in a system
regardless of the speed each cpu is running..
While nsecs would be nice even usecs might do.
They don't even have to be in sync as long as the offset
between them is constant (though that would be nice).
Bonus points for being able to read it from user space. The
hardware people don't seem to realise the importance
of this. and keep throwing it out to gain/save a pin or to save
some transistors for some other feature.
Received on Fri Apr 18 2008 - 15:54:48 UTC

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