Steve Kargl wrote: > > PS : is this an indication of bug in the p-III or in the chipset ? > > (ISTR these options could be used to get around unnamed errata of the p-IV) > > You'll need to search the mailing list archive for vague ramblings > by Terry Lambert about these option, large memory machines, > and bugs in the Intel CPUi architecture. Let me say *unequivocally* that *all* Intel and AMD CPUs that support PSE have this problem. The only thing memory size and specific CPU type have to do with it is in how hard it is to trigger the bug accidently. > I was hoping to avoid > Yet Another Terry Email (YATE) on the subject, which simply > tells us how clever he is without giving any details. NDA like Bosko and a half dozen others have, and I will send you the 6K file which describes the problem in great detail. -- TerryReceived on Tue Jul 08 2003 - 23:48:39 UTC
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