Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)?

From: Bruce M Simpson <bms_at_spc.org> Date: Wed, 16 Jun 2004 11:23:13 +0100 · This archive was generated by hypermail 2.4.0 : Wed May 19 2021 - 11:37:57 UTC

On Wed, Jun 16, 2004 at 11:11:02AM +0100, Bruce M Simpson wrote:
> On Wed, Jun 16, 2004 at 11:46:26AM +0200, Martin Nilsson wrote:
> > 
> > How much effct on performance does a wrong cache size value have?
> 
> Gag. I posted something on this whole subject last *year*, and still
> haven't gotten round to code.

http://www.usenix.org/publications/library/proceedings/als00/2000papers/papers/full_papers/sears/sears_html/

is a good starting point.

The points Dillon made this time last year on -hackers/in private mail
about mutex alignment on cache line boundaries also apply...

BMS