Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)?

On 2004.06.16 18:11, John Polstra wrote:
> On 16-Jun-2004 Alexander Leidinger wrote:
> 
>>Hi,
>>
>>I'm working with Alan and Chad David on automatic tuning of the number
>>of colors for the page queue. For AMD CPUs (including amd64, but not
>>tested) we already have code in identcpu.c to determine the size of the
>>L2 cache and its associativity.
>>
>>Now I need to know how to determine those properties on at least some
>>Intel CPUs (e.g. P3 & P4).
>>
>>Since Intel has a lot of manuals and everyone contains a lot of pages, I
>>decided to first ask here if someone can give me a pointer please (or
>>working code).
> 
> 
> Check out the "misc/cpuid" port.  Here's some sample output from a
> PIII system.  Cache information is at the end.
> 

The latest version of cpuid is from 2002 and at least for my Athlon XP-M 
processor it doesn't read the information about L2 cache correctly. 
IIRC, for my L2 size it only takes one byte from the beginning of ecx 
register, whereas in my case it is stored in two, a.s.o. So I wouldn't 
rely on cpuid when it comes to newer CPUs.

-Radek