: Hmm. I can think of two solutions that avoid masking: : : * Change the trigger mode from level to edge as a means of masking the : interrupt, then change it back to level triggered to unmask. This : would be done in the IO APIC. : : * Change the delivery mode to low-priority for the interrupt that occured : and use the priority field to mask the interrupt to the cpu. This : would be done in the IO APIC with the LAPIC's TPR set appropriately. Here's a third... mess with the IOART_DEST mask for the pin on the IOAPIC. Can it be set to not route the interrupt to *any* cpu ? Usually it's set to broadcast (all bits 1, at least on 4.x and DragonFly). so. e.g. IOART_DESTPHY but then with no cpu specified in IOART_DEST. -Matt Matthew Dillon <dillon_at_backplane.com>Received on Mon Apr 11 2005 - 05:15:33 UTC
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