Re: machdep.cpu_idle_hlt and SMP perf?

Andrew Gallatin wrote:

>Why dooes machdep.cpu_idle_hlt=1 drop my 10GbE network rx
>performance by a considerable amount (7.5Gbs -> 5.5Gbs)?
>
>I've (blindly) tried leaving machdep.cpu_idle_hlt=1 enabled
>and playing with the vast array of kern.sched.ipiwakeup.* sysctls,
>but receive performance remains limited to ~5.5Gb/sec or less.
>
>This is an 'AMD Athlon(tm) 64 X2 Dual Core Processor 3800+' running
>FreeBSD-current as of about one week ago.  The interrupt load is 
>about 22,000 device interrupts/sec (ithreaded).  Interestingly,
>the more I decrease the interrupt load by increasing the interrupt
>coalescing timer, the worse the machdep.cpu_idle_hlt=1 case does.
>
>Is this just a case of the wakeup IPI taking a long time or blocking
>on some lock?
>
>Drew
>
>PS: Here is what I mean:
>  
>
I am thinking if we can rewrite cpu idle code by using mwait instruction on
pentium4, it should reduce latency, I don't know if Athlon 64 supports this
instruction yet.

David Xu