On Thu, Jul 27, 2006 at 10:58:12AM -0400, John Baldwin wrote: > That these counters are for stats. :) You always have a race when reading the > amount, so you can choose what is "good enough" to satisfy the conflicting > requirements of "cheap" and "accurate". To me, the cheapness of add+adc > (compared to say, a cmpxchg8b loop with a branch, etc.) is worth it if you > have this rare race. You can work around the problem when reading - e.g. read twice and check the values are close. But is add + adc safe for update? What about the following: - processor 1 reads low32 as FFFFFFFF - processor 2 reads low32 as FFFFFFFF - processor 1 writes low32 as 00000000 and sets carry - processor 2 writes low32 as 00000000 and sets carry - processor 1 adds 1 to high32 - processor 2 adds 1 to high32 I'm not saying this sequence can definitely occur - I'm thinking from a general point of view, and I don't know the i386 instruction set. It just seems plausible. OTOH, if the above race can occur, it would imply that even a simple 32-bit counter update could lose counts. Regards, Brian.Received on Fri Jul 28 2006 - 10:15:31 UTC
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