Re: Freeze due to performance_cx_lowest=LOW

on 01/06/2006 22:04 John Baldwin said the following:
> On Tuesday 30 May 2006 23:19, Nate Lawson wrote:
>> Andriy Gapon wrote:
>>> on 29/05/2006 23:10 Nate Lawson said the following:
>>>> disable apic (hint.apic.0.disabled="1").  I isolated this a little while 
>>>> ago to the change to enable LAPIC timer.  However, there is currently no 
>>>> easy way to disable the LAPIC timer with APIC enabled so you have to 
>>>> disable APIC.  jhb_at_ and I have been discussing how to do this better but 
>>>> no easy answers apparently.
>>> I am not sure what I am talking about, but is it potentially possible to
>>> drive timer system by more than one clock, actively using the most
>>> precise of them at any particular moment ? So that if LAPIC timer stops
>>> i8254 can be used instead.
>> That requires mixed mode delivery -- i8254 on legacy PIC irq and APIC 
>> mode for other interrupts.  jhb_at_ just killed this and isn't eager to add 
>> it back.  I'll let him explain if he has more to add.
> 
> Namely that it is unreliable and expressly forbidden by the ACPI spec.
> 

Maybe I will say something too ignorant for this list, but is it
possible to drive hardclock with two interrupts (I haven't thought yet
how, though) and use RTC as the second interrupt source ?
I think that RTC/IRQ8 (usually) doesn't have problems associated with
8254 timer/IRQ0 and can be used without mixed mode.

-- 
Andriy Gapon