Peter Jeremy wrote: > On Wed, 2006-May-10 10:42:39 +0200, Suleiman Souhlal wrote: > >>That's not enough. On some CPUs (like the current Opterons), the TSC >>slows down when the CPU executes a HLT instruction, so if you want good >>accuracy, you'll need to take that into account too. > > > The CPU can't be executing any instructions whilst it's halted. All > you need to do is update the base time/TSC count between when you exit > halt and when you return to userland. > > Since most sane code doesn't call gettimeofday() multiple times per > tick, one option might be to unmap the page when the base data becomes > invalid and update/remap the page when it is first accessed. > Another way would be to catch the first rdtsc call after a HLT, and reset the TSC to a good value. You can do this by making rdtsc usable only in ring0, which will make any userland rdtsc generate a general protection fault. You have to be careful, though, because on some Intel CPUs, you can only change the lower 32 bits of the TSC (the upper 32 bits get reset to 0 every time you write to the TSC). We actually implemented this at work, on Linux, to make sure that the TSCs between every processor is synchronized, and it appears to work pretty well. -- SuleimanReceived on Wed May 10 2006 - 08:31:52 UTC
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