Over night my systems works well, only one message from network came up: nfe0: watchdog timeout (missed Tx interrupts) -- recovering nfe0: watchdog timeout (missed Tx interrupts) -- recovering In the morning I tried your patch for mii and PHY. Bootingverbose again gives me: nfe0: <NVIDIA nForce MCP55 Networking Adapter> port 0xb000-0xb007 mem 0xfbef3000-0xfbef3fff,0xfbefa800-0xfbefa8ff,0 xfbefa400-0xfbefa40f irq 22 at device 8.0 on pci0 nfe0: Reserved 0x1000 bytes for rid 0x10 type 3 at 0xfbef3000 nfe0: bpf attached nfe0: Ethernet address: 00:16:17:95:d9:7c miibus0: <MII bus> on nfe0 ciphy0: <VSC8601 10/100/1000TX PHY> PHY 1 on miibus0 ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto nfe0: [MPSAFE] nfe0: [FILTER] First, all seems to be ok. Network was up and connected. After a minute I lost connection and the following messages appeared: miibus0: unknown CICADA PHY model 2 miibus0: unknown CICADA PHY model 2 miibus0: unknown CICADA PHY model 2 nfe0: watchdog timeout (missed Tx interrupts) -- recovering nfe0: watchdog timeout (missed Tx interrupts) -- recovering nfe0: watchdog timeout (missed Tx interrupts) -- recovering nfe0: watchdog timeout (missed Tx interrupts) -- recovering ... Probably a little more work on the patches is needed? I am offline for the next ten hours. After that I could test any new version ;-) Thank you very much, Rainer Pyun YongHyeon schrieb: > On Tue, Mar 13, 2007 at 09:46:01AM +0900, To Rainer Hurling wrote: > > On Mon, Mar 12, 2007 at 10:41:40PM +0100, Rainer Hurling wrote: > > > Pyun YongHyeon, thank you for reply. > > > > > > Sorry for the late answer, but I have been on business trip. > > > > > > Pyun YongHyeon schrieb: > > > >On Sun, Mar 11, 2007 at 09:09:47AM +0100, Rainer Hurling wrote: > > > > > Pyun YongHyeon schrieb: > > > > > >[... SNIP ...] > > > > > > > > > > > >Did stock nfe(4) work on MCP55? > > > > > >(I'm not interested in how nve(4) works on MCP55.) > > > > > >I'm afraid MCP55 requires different programming. Searching archives > > > > > >for Linux forcedeth driver also reveals issues on MCP55 which is > > > > > >exactly the same issue I think. > > > > > >I'll let you know if I find a clue but it's hard to fix due to lack > > > > > >of MCP55 hardware and documentation. > > > > > > > > > > > > > > > Yes, nfe(4) works on MCP55, but with some strange behaviour, see below. > > > > > > > > > > I am working with FreeBSD 7.0-CURRENT from 03/07/2007 on MSI K9N Neo. > > > > > 'dmesg | grep nfe' gives me: > > > > > > > > > > nfe0: <NVIDIA nForce MCP55 Networking Adapter> port 0xb000-0xb007 mem > > > > > 0xfbef7000-0xfbef7fff,0xfbefa800-0xfbefa8ff,0xfbefa400-0xfbefa40f irq 21 > > > > > at device 8.0 on pci0 > > > > > miibus0: <MII bus> on nfe0 > > > > > ukphy0: <Generic IEEE 802.3u media interface> PHY 1 on miibus0 > > > > > ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, > > > > > 1000baseT-FDX, auto > > > > > nfe0: using obsoleted if_watchdog interface > > > > > nfe0: Ethernet address: xx:xx:xx:xx:xx:xx > > > > > nfe0: [ITHREAD] > > > > > > > > > > It seems that there is a problem with watchdog. Perhaps the choosen > > > > > media interface ukphy0 is not correct? > > > > > > > > > > > > >Normally nVidia GigEs use Marvell PHY which is served by e1000phy(4) > > > >so I guess power saving mode had ukphy attach the PHY. > > > >Booting/loading module with bootverbose mode will show up OUI/model/rev > > > >of the PHY. Please let me know the OUI/model/rev output of ukphy(4). > > > > > > for ukphy0 bootverbose gives me : > > > > > > OUI 0x0001c1 model 0x0002 rev. 0 > > > > > > > Hmm, it's gigabit PHY from Vitesse semiconductor. > > AFAIK there is no driver for the PHY but I guess ciphy(4) would be a > > possible driver for the PHY. I've checked Vitesse site for the PHY > > documentation but it seems they require a kind of NDA and it's not > > available option to me. > > > > Please try attached patch and rebuild miibus(4) and give it a spin. > > > > Oops, please use this patch. > > > > ------------------------------------------------------------------------ > > Index: miidevs > =================================================================== > RCS file: /home/ncvs/src/sys/dev/mii/miidevs,v > retrieving revision 1.41 > diff -u -r1.41 miidevs > --- miidevs 21 Feb 2007 18:17:44 -0000 1.41 > +++ miidevs 13 Mar 2007 00:53:47 -0000 > _at__at_ -66,6 +66,7 _at__at_ > oui SIS 0x00e006 Silicon Integrated Systems > oui TDK 0x00c039 TDK > oui TI 0x080028 Texas Instruments > +oui VITESSE 0x0001c1 Vitesse Semiconductor > oui XAQTI 0x00e0ae XaQti Corp. > oui MARVELL 0x005043 Marvell Semiconductor > oui xxMARVELL 0x000ac2 Marvell Semiconductor > _at__at_ -135,6 +136,7 _at__at_ > > /* Cicada Semiconductor PHYs (now owned by Vitesse?) */ > model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY > +model VITESSE VSC8601 0x0002 VSC8601 10/100/1000TX PHY > model CICADA CS8201A 0x0020 Cicada CS8201 10/100/1000TX PHY > model CICADA CS8201B 0x0021 Cicada CS8201 10/100/1000TX PHY > > Index: ciphy.c > =================================================================== > RCS file: /home/ncvs/src/sys/dev/mii/ciphy.c,v > retrieving revision 1.8 > diff -u -r1.8 ciphy.c > --- ciphy.c 2 Dec 2006 19:36:25 -0000 1.8 > +++ ciphy.c 13 Mar 2007 00:53:47 -0000 > _at__at_ -91,6 +91,7 _at__at_ > MII_PHY_DESC(CICADA, CS8201), > MII_PHY_DESC(CICADA, CS8201A), > MII_PHY_DESC(CICADA, CS8201B), > + MII_PHY_DESC(VITESSE, VSC8601), > MII_PHY_END > }; > > _at__at_ -339,7 +340,24 _at__at_ > static void > ciphy_reset(struct mii_softc *sc) > { > + struct mii_data *mii; > + uint16_t val; > > + mii = sc->mii_pdata; > + if (strcmp(mii->mii_ifp->if_dname, "nfe") == 0) { > + /* need to set for 2.5V RGMII for NVIDIA adapters */ > + val = PHY_READ(sc, CIPHY_MII_ECTL1); > + val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); > + val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); > + PHY_WRITE(sc, CIPHY_MII_ECTL1, val); > + /* From Linux. */ > + val = PHY_READ(sc, CIPHY_MII_AUXCSR); > + val |= CIPHY_AUXCSR_MDPPS; > + PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); > + val = PHY_READ(sc, CIPHY_MII_10BTCSR); > + val |= CIPHY_10BTCSR_ECHO; > + PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); > + } > mii_phy_reset(sc); > DELAY(1000); > } > Index: ciphyreg.h > =================================================================== > RCS file: /home/ncvs/src/sys/dev/mii/ciphyreg.h,v > retrieving revision 1.2 > diff -u -r1.2 ciphyreg.h > --- ciphyreg.h 6 Jan 2005 01:42:55 -0000 1.2 > +++ ciphyreg.h 13 Mar 2007 00:53:47 -0000 > _at__at_ -251,6 +251,16 _at__at_ > /* Extended PHY control register #1 */ > #define CIPHY_MII_ECTL1 0x17 > #define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ > +#define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */ > +#define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */ > + > +#define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */ > +#define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */ > + > +#define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */ > +#define CIPHY_INTSEL_RGMII 0x1000 > +#define CIPHY_INTSEL_TBI 0x2000 > +#define CIPHY_INTSEL_RTBI 0x3000 > > /* Extended PHY control register #2 */ > #define CIPHY_MII_ECTL2 0x18Received on Tue Mar 13 2007 - 04:29:33 UTC
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