Re: TSC Timecounter and multi-core/SMP

From: Julian Elischer <julian_at_elischer.org>
Date: Thu, 10 Apr 2008 09:23:49 -0700
Matthew Dillon wrote:
>   
> :Howdy,
> :
> :Is the TSC timecounter synchronized across multiple cores and/or
> :processors?  A quick search seems to indicate it's not but I'd like to
> :find a definitive reference on the TSC.
> :
> :Thanks,
> :George
> 
>     At least on AMD X2 boxes they are not synchronized.  The absolute
>     values of the TSC counters will be off and they will also drift
>     relative to each other, which can readily be demonstrated with some 
>     test IPIs on DragonFly with the TSC synchronization code turned off.
> 
>     In these tests a single IPI is sent from one cpu to another and
>     the absolute value of each cpu's TSC is recorded.  The number in the
>     parenthesis is the difference between the two absolute values.
> 
>     The difference should be about the same same when the test is repeated,
>     but as you can see the gap increases in each successive test.
> 
> index  cpu timestamp        ID                   trace
>  0140bb 0   1083883698618    testlog_pingpong     pingpong	(720862)
>  00f619 1   1083882977756    testlog_pingpong     pingpong
> 
>  0140bc 0   1143172876697    testlog_pingpong     pingpong	(768494)
>  00f61a 1   1143172108203    testlog_pingpong     pingpong
> 
>  0140bd 0   1164275800252    testlog_pingpong     pingpong	(785266)
>  00f61b 1   1164275014986    testlog_pingpong     pingpong
> 
>  0140be 0   1179148341147    testlog_pingpong     pingpong	(799137)
>  00f61c 1   1179147542010    testlog_pingpong     pingpong
> 
>     So not only are the TSC's not synchronized with each other, but their
>     frequencies are also not locked relative to each other.  There will
>     a small amount of drift for each cpu and I'm guessing the dift will
>     also slide around a bit based on temperature.
> 
>     Intel might work differently but I don't have any intel multi-cores
>     handy to run the test on so I don't know.


Someone once told me that there was some complication WRT
the TSC and SMI interrupts too.. though I can't remember what it
was exactly.. I do however remember thinking "That's insane!"



> 
> 					-Matt
> 					Matthew Dillon 
> 					<dillon_at_backplane.com>
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Received on Thu Apr 10 2008 - 14:23:51 UTC

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