Re: TSC Timecounter and multi-core/SMP

On Thursday 10 April 2008 06:21 pm, Gary Stanley wrote:
> At 05:45 PM 4/10/2008, Poul-Henning Kamp wrote:
> >In message <47FE7E0C.4070801_at_FreeBSD.org>, Maxim Sobolev writes:
> > >Kris Kennaway wrote:
> > >> gnn_at_freebsd.org wrote:
> > >>> Howdy,
> > >>>
> > >>> Is the TSC timecounter synchronized across multiple cores
> > >>> and/or processors?  A quick search seems to indicate it's not
> > >>> but I'd like to find a definitive reference on the TSC.
> > >>
> > >> Modern Intel systems tend to be synchronized, in my
> > >> experience.
> > >
> > >I really doubt they are. As far as I know newest milti-core
> > > chips can modulate frequency of even suspend individual cores
> > > independently of each other, which would make such
> > > synchronization difficult to maintain if the power management
> > > is on.
> >
> >P4 (and I think most newer chips) have a TSC that runs independent
> >of the cpu clock frequency, and supposedly, always at constant
> > rate.
>
> Are you talking about the RDTSCP? I think its only on newer
> opterons and phenoms.

I think you got it confused with "TscInvariant" feature:

http://ltt.polymtl.ca/svn/ltt/branches/poly/doc/developer/tsc.txt

"Because using the TSC for fast timer APIs is a desirable feature that 
helps performance, AMD has defined a CPUID feature bit that software 
can test to determine if the TSC is invariant. Issuing a CPUID 
instruction with an %eax register value of  0x8000_0007, on a 
processor whose base family is 0xF, returns "Advanced Power 
Management Information" in the %eax, %ebx, %ecx, and %edx registers. 
Bit 8 of the return %edx is the "TscInvariant" feature flag which is 
set when TSC is P-state, C-state, and STPCLK-throttling invariant; it 
is clear otherwise."

RDTSCP is not P-state invariant.  RDTSCP returns CPU ID with it, 
nothing more.  Even if you have TscInvariant CPUs, I am not sure TSCs 
between cores/packages are synchronized.

Jung-uk Kim