So the real fix is that we need to disable memory and I/O decoding int the PCI command register when messing with the BARs. One thing to be careful with is we can't do any console I/O (i.e. printfs) while the BAR is disabled. I will come up with a proper patch when I get back to a real computer. -- John Baldwin On Dec 13, 2008, at 10:51 PM, Tor Egge <Tor.Egge_at_cvsup.no.freebsd.org> wrote: >> Well, we probably need to come up with a better way to determine >> which >> machines to actually use it on. It's a shame that MCFG is >> apparently busted >> on so many machines (either that or we are not doing something >> correctly). > > pci_add_map() writes 0xffffffff to the map register in order to > probe for > writable bits. This had the immediate side effect of hanging my > machine. > Since I didn't know about the "Add hw.pci.mcfg=0 to /boot/ > loader.conf" at that > time, I started using the enclosed kludgy patch (specific for Intel > 82Q33 > hardware). Only the GMADDR map register was a problem. > > It looks like the graphics memory aperture was mapped on top of the > memory > mapped pci config registers, thus only IO access to the pci config > registers > worked to undo the supposedly temporary change. > > - Tor Egge > Index: sys/conf/options > =================================================================== > RCS file: /home/ncvs/src/sys/conf/options,v > retrieving revision 1.651 > diff -u -r1.651 options > --- sys/conf/options 11 Dec 2008 16:13:17 -0000 1.651 > +++ sys/conf/options 12 Dec 2008 20:00:11 -0000 > _at__at_ -786,3 +786,7 _at__at_ > # Virtualize the network stack > VIMAGE opt_global.h > VIMAGE_GLOBALS opt_global.h > + > +# Kludge to work around hangs during probing of Intel 82Q33 PCI > devices > +# (vendor 0x8086, device 0x29d2). > +PCI_INTEL_82Q33_KLUDGE opt_kludge.h > Index: sys/dev/pci/pci.c > =================================================================== > RCS file: /home/ncvs/src/sys/dev/pci/pci.c,v > retrieving revision 1.366 > diff -u -r1.366 pci.c > --- sys/dev/pci/pci.c 13 Nov 2008 19:57:33 -0000 1.366 > +++ sys/dev/pci/pci.c 14 Nov 2008 18:27:31 -0000 > _at__at_ -30,6 +30,7 _at__at_ > __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.366 2008/11/13 > 19:57:33 mav Exp $"); > > #include "opt_bus.h" > +#include "opt_kludge.h" > > #include <sys/param.h> > #include <sys/systm.h> > _at__at_ -2289,11 +2290,52 _at__at_ > int type; > int barlen; > struct resource *res; > +#ifdef PCI_INTEL_82Q33_KLUDGE > + struct pci_devinfo *dinfo; > + pcicfgregs *cfg; > + uint32_t msacval; > +#endif > > map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); > +#ifdef PCI_INTEL_82Q33_KLUDGE > + dinfo = device_get_ivars(dev); > + cfg = &dinfo->cfg; > + /* > + * The test write to probe for writable address bits hangs > + * some machines. Kludge around this by faking the test based > + * on the MSAC register at offset 0x62. Intel doc is slightly > + * inconsistent about which bits in MSAC controls the aperture > + * size. > + */ > + if (cfg->vendor == 0x8086 && cfg->device == 0x29d2 && reg == > 24) { > + printf("Kludge: " > + "faking test to avoid hang for 82Q33 GMADDR config > \n"); > + msacval = PCIB_READ_CONFIG(pcib, b, s, f, 0x62, 1); > + printf("82Q33 MSAC (offset 0x62) val is 0x%02x\n", msacval); > + switch ((msacval >> 1) & 3) { > + case 0: > + testval = 0xf8000008u; > + break; > + case 1: > + testval = 0xf0000008u; > + break; > + case 3: > + testval = 0xe0000008u; > + break; > + default: > + printf("BAD MSAC val\n"); > + testval = 0xe0000008u; > + break; > + } > + goto kludgedone; > + } > +#endif > PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); > testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); > PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); > +#ifdef PCI_INTEL_82Q33_KLUDGE > +kludgedone: > +#endif > > if (PCI_BAR_MEM(map)) > type = SYS_RES_MEMORY;Received on Tue Dec 16 2008 - 14:18:43 UTC
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