Re: issues with hwpmc and athlon XP

On 10/03/2008, Adrian Chadd <adrian_at_freebsd.org> wrote:
> Between my Athlon XP box giving me no useful pmc stats and my new Core
>  2 duo box not even working with pmc, I decided to poke at the Athlon
>  XP support a bit to see if I could figure out what was going on.

Here's an updated patch. It seems to be returning the system CPU usage
I expect in my profile but I still don't get any useful usermode
sampling. I'll dig deeper into that to try and figure out whats going
on.

It fixes a debugging output issue (which I'm happy to commit
seperately) and it "sign-extends" the 48 value read back from the AMD
counter to a 64 bit value to preserve the 2s compliment semantics that
is used for the "count up to overflow NMI" trick.

jkoshy, do you mind if I commit this and then MFC it to RELENG_7?

Thanks,


Adrian

Index: hwpmc_amd.c
===================================================================
RCS file: /share/FreeBSD/cvsrepo/src/sys/dev/hwpmc/hwpmc_amd.c,v
retrieving revision 1.14
diff -u -r1.14 hwpmc_amd.c
--- hwpmc_amd.c 7 Dec 2007 08:20:15 -0000       1.14
+++ hwpmc_amd.c 16 Mar 2008 05:02:38 -0000
_at__at_ -302,12 +302,22 _at__at_
 #endif

        tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
-       if (PMC_IS_SAMPLING_MODE(mode))
-               *v = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
-       else
-               *v = tmp;
+       PMCDBG(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
+       if (PMC_IS_SAMPLING_MODE(mode)) {
+               /*
+                * The counters are 48 bit but we expect them to be 64 bit for
+                * 2s compliment "hack" done to allow the "count up" to overflow
+                * which triggers the sampling mode NMI.
+                * This code sign-extends the 48 bit number in case the returned
+                * value requires it.
+                */
+               if (tmp & 0x0000800000000000)
+                       tmp |= 0xffff000000000000;
+               tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
+       }
+       *v = tmp;

-       PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v);
+       PMCDBG(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);

        return 0;
 }
_at__at_ -683,7 +693,7 _at__at_
        KASSERT(cpu >= 0 && cpu < mp_ncpus,
            ("[amd,%d] out of range CPU %d", __LINE__, cpu));

-       PMCDBG(MDP,INT,1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
+       PMCDBG(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
            TRAPF_USERMODE(tf));

        retval = 0;