Re: Improving the kernel/i386 timecounter performance (GSoC proposal)

On Sun, Mar 29, 2009 at 2:07 PM, Peter Jeremy
<peterjeremy_at_optushome.com.au> wrote:
> On 2009-Mar-27 14:19:16 -0400, Alexander Sack <pisymbol_at_gmail.com> wrote:
>>I'm assuming folks are still in love with the TSC because it still the
>>cheapest as oppose ACPI-fast or HPET to even contemplate this?
>
> That is its major advantage.  It might be feasible to export all the
> data necessary to implement the complete CLOCK_*_FAST family.

Understood.

>>Also I thought at least PHK's comment (Sergey mentioned it) was true
>>regardless of bus, that the TSC is not consistent across multiple
>>packages (and for that matter I suppose cores) due to I *think* its
>>ISA lineage so how does this work again?
>
> TSC is nothing to do with ISA.  The easiest way to build a counter
> that runs at CPU clock rate is to put it very close to the CPU/core
> and have different counters for each CPU/core, without any
> synchronisation between the different counters.

Understood thanks.  I don't know why ISA and TSC are in my head.  Please excuse.

>>  Won't the rate in which you
>>tick up be sporadic over the course of the process scheduled on
>>different cores?  (i.e. depending on what core RDTSC happened to land
>>on)
>
> RDTSC will wind up on the same core that your thread of execution is
> running on and this is defined by the scheduler.  IE, it's up to the
> scheduler to ensure that the correct page of global (or per-cpu) data
> is mapped.

OK.  But then why not do what I *think* Solaris does in the first
place, sync the cores using a master/slave to effectively create an
invariant TSC i.e if you are going to buy the overhead in the
scheduler why not do the dirty work at the source instead of all this
overhead in either the scheduler or the logic to know that this thread
of execution was on that core and is using this TSC etc. etc.

I believe this topic has been re-hashed before I don't remember the
outcome so again excuse... :D

Thanks!

-aps