Re: 8.0RC2 amd64 - kernel panic running make buildworld

Kai, Serguey,

thank you very much for the testing!
This has been an invaluable help.

I am now trying to narrow down possible causes of the issue and to come up with
the most efficient patch.

If/when you have a chance could you please test the following changes?
The patches are against mainline source tree (that is, not against previous
patch(es)).

So, please first try *only* this patch:
diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c
index 44b71f3..33b8c2a 100644
--- a/sys/amd64/amd64/pmap.c
+++ b/sys/amd64/amd64/pmap.c
_at__at_ -2981,6 +2981,7 _at__at_ setpte:
 	 * Map the superpage.
 	 */
 	pde_store(pde, PG_PS | newpde);
+	pmap_invalidate_range(pmap, trunc_2mpage(va), trunc_2mpage(va) + NBPDR);

 	pmap_pde_promotions++;
 	CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"

Most likely this will fix the buildworld scenario.
But I am not sure if it will fix ZFS scenario.
If it does - then great, if not, please apply the following patch in addition to
the previous one and test again:

diff --git a/sys/amd64/amd64/mca.c b/sys/amd64/amd64/mca.c
index d291d00..d6547a3 100644
--- a/sys/amd64/amd64/mca.c
+++ b/sys/amd64/amd64/mca.c
_at__at_ -43,6 +43,7 _at__at_ __FBSDID("$FreeBSD$");
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <sys/taskqueue.h>
+#include <machine/cputypes.h>
 #include <machine/mca.h>
 #include <machine/md_var.h>
 #include <machine/specialreg.h>
_at__at_ -465,6 +466,8 _at__at_ void
 mca_init(void)
 {
 	uint64_t mcg_cap;
+	uint64_t ctl;
+	int skip;
 	int i;

 	/* MCE is required. */
_at__at_ -482,14 +485,22 _at__at_ mca_init(void)
 			wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);

 		for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
-			/*
-			 * Enable logging of all errors.  For P6
-			 * processors, MC0_CTL is always enabled.
-			 *
-			 * XXX: Better CPU test needed here?
-			 */
-			if (!(i == 0 && (cpu_id & 0xf00) == 0x600))
-				wrmsr(MSR_MC_CTL(i), 0xffffffffffffffffUL);
+			/* By default enable logging of all errors. */
+			ctl = 0xffffffffffffffffUL;
+			skip = 0;
+			if (cpu_vendor_id == CPU_VENDOR_INTEL) {
+				/* For P6 MC0_CTL is always enabled. */
+				if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6)
+					skip = 1;
+			} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
+				/* BKDG for Family 10h: unset GartTblWkEn. */
+				if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf) {
+					ctl &= ~(1UL << 10);
+				}
+			}
+
+			if (!skip)
+				wrmsr(MSR_MC_CTL(i), ctl);

 			/* Clear all errors. */
 			wrmsr(MSR_MC_STATUS(i), 0);


-- 
Andriy Gapon