MCP55 SATA solution to test

Hi.

Thanks to one man who provided access to his machine, I seem to found
how to fix device detection on nVidia MCP55 SATA controller on amd64
8.0. Looks like this controller need some time (very short) to enable
BAR(5) memory access after PCI configuration register written. Probably
some changes in PCI code exposed this issue. Also it explains why
setting hw.pci.mcfg to 0 helps.

Attached patch solves problem for that machine. Testers are welcome.

-- 
Alexander Motin

--- ata-nvidia.c.prev	2009-10-25 03:13:57.000000000 +0300
+++ ata-nvidia.c	2009-10-25 03:15:52.000000000 +0300
_at__at_ -165,7 +165,8 _at__at_ ata_nvidia_chipinit(device_t dev)
 
 	    /* enable control access */
 	    pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
-
+	    /* MCP55 seems to need some time to allow r_res2 read. */
+	    DELAY(10);
 	    if (ctlr->chip->cfg1 & NVQ) {
 		/* clear interrupt status */
 		ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);