Re: [INFO]: import of clang/LLVM to happen on June 9th

Doug Barton <dougb_at_FreeBSD.org> writes:

> On 06/04/10 17:38, Doug Barton wrote:
>> On 06/04/10 11:28, Andrius Morkūnas wrote:
>>
>>> http://www.freebsd.org/doc/en_US.ISO8859-1/articles/custom-gcc/configuring-ports-gcc.html
>
> Ok, everything in that section seems clear except this in 3.3:
> It is possible to completely replace CFLAGS and/or define custom
> CPUTYPE as well. We recommend setting CPUTYPE because many ports
> decide their optimizations flags based on this variable.

Most ports decide features based on MACHINE_CPU not CPUTYPE. However,
MACHINE_CPU doesn't support non-base compiler and `native' CPUTYPE. Plus
core2 CPUTYPE is silently degraded to nocona/prescott even when it's
supported by underlying compiler. See conf/112997.

>
> How do I figure out what to set for CPUTYPE? Also, what else should I
> include in CFLAGS besides -mssse3?  I have a core 2 duo processor,

IIRC, on gcc44+ -march=native automatically enables -msse[1234].
But if you don't want to use CPUTYPE=native then add cc1 flags to
CFLAGS, e.g.

  $ gcc45 -E -v -march=native - </dev/null |& sed -nE 's/.*cc1 -E -quiet -v (- )?//p'
  -march=core2 -mcx16 -msahf -msse4.1 --param l1-cache-size=32 --param l1-cache-line-size=64 --param l2-cache-size=6144 -mtune=core2

> which says this at boot time:
> CPU: Intel(R) Core(TM)2 CPU         T7600  _at_ 2.33GHz (2330.23-MHz
> 686-class CPU)
>   Origin = "GenuineIntel"  Id = 0x6f6  Family = 6  Model = f  Stepping = 6
>
> Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
>   Features2=0xe3bd<SSE3,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM>
>   AMD Features=0x20100000<NX,LM>
>   AMD Features2=0x1<LAHF>
>   TSC: P-state invariant
>
>
> Thanks!
>
> Doug