Another system: CPU: Intel(R) Core(TM) i7-3770 CPU _at_ 3.40GHz (3392.36-MHz K8-class CPU) Origin = "GenuineIntel" Id = 0x306a9 Family = 6 Model = 3a Stepping = 9 Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> Features2=0x7fbae3ff<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,AVX,F16C,RDRAND> AMD Features=0x28100800<SYSCALL,NX,RDTSCP,LM> AMD Features2=0x1<LAHF> TSC: P-state invariant, performance statistics All pmcstat tests worked. The pmctest.py script failed with SOFT the same way as bapt_at_'s, but all subsequent tests passed. pmccontrol -L output appended. later, Peter. # ./pmccontrol -L SOFT CLOCK.STAT CLOCK.HARD LOCK.FAILED PAGE_FAULT.WRITE PAGE_FAULT.READ PAGE_FAULT.ALL TSC TSC IAP LD_BLOCKS.STORE_FORWARD MISALIGN_MEM_REF.LOADS MISALIGN_MEM_REF.STORES LD_BLOCKS_PARTIAL.ADDRESS_ALIAS DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION UOPS_ISSUED.ANY UOPS_ISSUED.FLAGS_MERGE UOPS_ISSUED.SLOW_LEA UOPS_ISSUED.SINGLE_MUL ARITH.FPU_DIV_ACTIVE L2_RQSTS.DEMAND_DATA_RD_HIT L2_RQSTS.ALL_DEMAND_DATA_RD L2_RQSTS.RFO_HITS L2_RQSTS.RFO_MISS L2_RQSTS.ALL_RFO L2_RQSTS.CODE_RD_HIT L2_RQSTS.CODE_RD_MISS L2_RQSTS.ALL_CODE_RD L2_RQSTS.PF_HIT L2_RQSTS.PF_MISS L2_RQSTS.ALL_PF L2_STORE_LOCK_RQSTS.MISS L2_STORE_LOCK_RQSTS.HIT_M L2_STORE_LOCK_RQSTS.ALL L2_L1D_WB_RQSTS.MISS L2_L1D_WB_RQSTS.HIT_E L2_L1D_WB_RQSTS.HIT_M L2_L1D_WB_RQSTS.ALL LONGEST_LAT_CACHE.REFERENCE LONGEST_LAT_CACHE.MISS CPU_CLK_UNHALTED.THREAD_P CPU_CLK_THREAD_UNHALTED.REF_XCLK L1D_PEND_MISS.PENDING DTLB_STORE_MISSES.MISS_CAUSES_A_WALK DTLB_STORE_MISSES.WALK_COMPLETED DTLB_STORE_MISSES.WALK_DURATION DTLB_STORE_MISSES.STLB_HIT LOAD_HIT_PRE.SW_PF LOAD_HIT_PRE.HW_PF L1D.REPLACEMENT MOVE_ELIMINATION.INT_NOT_ELIMINATED MOVE_ELIMINATION.SIMD_NOT_ELIMINATED MOVE_ELIMINATION.INT_ELIMINATED MOVE_ELIMINATION.SIMD_ELIMINATED CPL_CYCLES.RING0 CPL_CYCLES.RING123 RS_EVENTS.EMPTY_CYCLES TLB_ACCESS.LOAD_STLB_HIT OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION LOCK_CYCLES.CACHE_LOCK_DURATION IDQ.EMPTY IDQ.MITE_UOPS IDQ.DSB_UOPS IDQ.MS_DSB_UOPS IDQ.MS_MITE_UOPS IDQ.MS_UOPS IDQ.ALL_DSB_CYCLES_ANY_UOPS IDQ.ALL_DSB_CYCLES_4_UOPS IDQ.ALL_MITE_CYCLES_ANY_UOPS IDQ.ALL_MITE_CYCLES_4_UOPS IDQ.MITE_ALL_UOPS ICACHE.MISSES ITLB_MISSES.MISS_CAUSES_A_WALK ITLB_MISSES.WALK_COMPLETED ITLB_MISSES.WALK_DURATION ITLB_MISSES.STLB_HIT ILD_STALL.LCP ILD_STALL.IQ_FULL BR_INST_EXEC.COND BR_INST_EXEC.DIRECT_JMP BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET BR_INST_EXEC.RETURN_NEAR BR_INST_EXEC.DIRECT_NEAR_CALL BR_INST_EXEC.INDIRECT_NEAR_CALL BR_INST_EXEC.NONTAKEN BR_INST_EXEC.TAKEN BR_INST_EXEC.ALL_BRANCHES BR_MISP_EXEC.COND BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET BR_MISP_EXEC.RETURN_NEAR BR_MISP_EXEC.DIRECT_NEAR_CALL BR_MISP_EXEC.INDIRECT_NEAR_CALL BR_MISP_EXEC.NONTAKEN BR_MISP_EXEC.TAKEN BR_MISP_EXEC.ALL_BRANCHES IDQ_UOPS_NOT_DELIVERED.CORE UOPS_DISPATCHED_PORT.PORT_0 UOPS_DISPATCHED_PORT.PORT_1 UOPS_DISPATCHED_PORT.PORT_2_LD UOPS_DISPATCHED_PORT.PORT_2_STA UOPS_DISPATCHED_PORT.PORT_2 UOPS_DISPATCHED_PORT.PORT_3_LD UOPS_DISPATCHED_PORT.PORT_3_STA UOPS_DISPATCHED_PORT.PORT_3 UOPS_DISPATCHED_PORT.PORT_4 UOPS_DISPATCHED_PORT.PORT_5 RESOURCE_STALLS.ANY RESOURCE_STALLS.RS RESOURCE_STALLS.SB RESOURCE_STALLS.ROB DSB2MITE_SWITCHES.COUNT DSB2MITE_SWITCHES.PENALTY_CYCLES DSB_FILL.EXCEED_DSB_LINES ITLB.ITLB_FLUSH OFFCORE_REQUESTS.DEMAND_DATA_RD OFFCORE_REQUESTS.DEMAND_CODE_RD OFFCORE_REQUESTS.DEMAND_RFO OFFCORE_REQUESTS.ALL_DATA_RD UOPS_EXECUTED.THREAD UOPS_EXECUTED.CORE OFF_CORE_RESPONSE_0 OFF_CORE_RESPONSE_1 TLB_FLUSH.DTLB_THREAD TLB_FLUSH.STLB_ANY INST_RETIRED.ANY_P INST_RETIRED.ALL OTHER_ASSISTS.AVX_STORE OTHER_ASSISTS.AVX_TO_SSE OTHER_ASSISTS.SSE_TO_AVX UOPS_RETIRED.ALL UOPS_RETIRED.RETIRE_SLOTS MACHINE_CLEARS.MEMORY_ORDERING MACHINE_CLEARS.SMC MACHINE_CLEARS.MASKMOV BR_INST_RETIRED.ALL_BRANCHES BR_INST_RETIRED.CONDITIONAL BR_INST_RETIRED.NEAR_CALL BR_INST_RETIRED.ALL_BRANCHES BR_INST_RETIRED.NEAR_RETURN BR_INST_RETIRED.NOT_TAKEN BR_INST_RETIRED.NEAR_TAKEN BR_INST_RETIRED.FAR_BRANCH BR_MISP_RETIRED.ALL_BRANCHES BR_MISP_RETIRED.CONDITIONAL BR_MISP_RETIRED.NEAR_CALL BR_MISP_RETIRED.ALL_BRANCHES BR_MISP_RETIRED.NOT_TAKEN BR_MISP_RETIRED.TAKEN FP_ASSIST.X87_OUTPUT FP_ASSIST.X87_INPUT FP_ASSIST.SIMD_OUTPUT FP_ASSIST.SIMD_INPUT FP_ASSIST.ANY ROB_MISC_EVENTS.LBR_INSERTS MEM_TRANS_RETIRED.LOAD_LATENCY MEM_TRANS_RETIRED.PRECISE_STORE MEM_UOP_RETIRED.LOADS MEM_UOP_RETIRED.STORES MEM_UOP_RETIRED.STLB_MISS MEM_UOP_RETIRED.LOCK MEM_UOP_RETIRED.SPLIT MEM_UOP_RETIRED.ALL MEM_LOAD_UOPS_RETIRED.L1_HIT MEM_LOAD_UOPS_RETIRED.L2_HIT MEM_LOAD_UOPS_RETIRED.LLC_HIT MEM_LOAD_UOPS_RETIRED.HIT_LFB MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM L2_TRANS.DEMAND_DATA_RD L2_TRANS.RFO L2_TRANS.CODE_RD L2_TRANS.ALL_PF L2_TRANS.L1D_WB L2_TRANS.L2_FILL L2_TRANS.L2_WB L2_TRANS.ALL_REQUESTS L2_LINES_IN.I L2_LINES_IN.S L2_LINES_IN.E L2_LINES_IN.ALL L2_LINES_OUT.DEMAND_CLEAN L2_LINES_OUT.DEMAND_DIRTY L2_LINES_OUT.PF_CLEAN L2_LINES_OUT.PF_DIRTY IAF INSTR_RETIRED_ANY CPU_CLK_UNHALTED_CORE CPU_CLK_UNHALTED_REFReceived on Wed Sep 05 2012 - 16:12:39 UTC
This archive was generated by hypermail 2.4.0 : Wed May 19 2021 - 11:40:30 UTC