Re: hwpmc support for haswell

On Sat, Mar 23, 2013 at 8:58 AM, hiren panchasara
<hiren.panchasara_at_gmail.com> wrote:
>
> On Mar 22, 2013 10:48 PM, "Jim Harris" <jim.harris_at_gmail.com> wrote:
>>
>>
>>
>> On Friday, March 22, 2013, hiren panchasara wrote:
>>>
>>> On Thu, Jan 31, 2013 at 6:26 PM, hiren panchasara
>>> <hiren.panchasara_at_gmail.com> wrote:
>>> > On Thu, Jan 31, 2013 at 5:47 PM, Davide Italiano <davide_at_freebsd.org>
>>> > wrote:
>>> >> On Fri, Feb 1, 2013 at 2:17 AM, hiren panchasara
>>> >> <hiren.panchasara_at_gmail.com> wrote:
>>> >>> Hi,
>>> >>>
>>> >>> I've prepared a patch to add core and uncore events support for
>>> >>> haswell processor.
>>> >>> I do not have the hardware to test this. It applies cleanly and
>>> >>> compiles fine though.
>>> >>>
>>> >>> http://www.strugglingcoder.info/patches/hwpmc_hw.txt
>>> >>>
>>> >>> This is initial version of patch and manpage is still missing. I will
>>> >>> add it in a few days.
>>> >>>
>>> >>> Any help in testing is appreciated.
>>> >>>
>>> >>> Thanks,
>>> >>> Hiren
>>> >>
>>> >> It seems Intel won't release this before June (at least to my
>>> >> knowledge).
>>> >> I would claim it'll be difficult to real test this before that date
>>> >> unless someone has prerelease hardware.
>>> >
>>> > Indeed. I've posted it here just to let larger audience know and avoid
>>> > possible duplicate work.
>>> >
>>> > We will wait till we get the hardware to test with.
>>>
>>> I recently got a ref haswell box to play with.
>>>
>>> Initial dmesg looks like this:
>>>
>>> CPU: Genuine Intel(R) CPU 0000 _at_ 2.60GHz (2594.05-MHz K8-class CPU)
>>>   Origin = "GenuineIntel"  Id = 0x306c2  Family = 0x6  Model = 0x3c
>>> Stepping = 2
>>>
>>> Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
>>>
>>> Features2=0x7ffafbff<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,SMX,EST,TM2,SSSE3,<b11>,FMA,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,AVX,F16C,RDRAND>
>>>   AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
>>>   AMD Features2=0x21<LAHF,ABM>
>>>   Standard Extended
>>> Features=0x2fbb<GSFSBASE,TSCADJ,SMEP,ENHMOVSB,INVPCID>
>>>   TSC: P-state invariant, performance statistics
>>> real memory  = 8589934592 (8192 MB)
>>> avail memory = 8034803712 (7662 MB)
>>> Event timer "LAPIC" quality 600
>>> ACPI APIC Table: <DELL   CBX3   >
>>> FreeBSD/SMP: Multiprocessor System Detected: 8 CPUs
>>> FreeBSD/SMP: 1 package(s) x 4 core(s) x 2 SMT threads
>>>  cpu0 (BSP): APIC ID:  0
>>>  cpu1 (AP): APIC ID:  1
>>>  cpu2 (AP): APIC ID:  2
>>>  cpu3 (AP): APIC ID:  3
>>>  cpu4 (AP): APIC ID:  4
>>>  cpu5 (AP): APIC ID:  5
>>>  cpu6 (AP): APIC ID:  6
>>>  cpu7 (AP): APIC ID:  7
>>>
>>> Diffs at:
>>> http://www.strugglingcoder.info/patches/hwpmc_hw.txt
>>> Tests I've done:
>>> http://www.strugglingcoder.info/patches/hwpmc_hw_pmccontrol.txt
>>> http://www.strugglingcoder.info/patches/hwpmc_hw_pmctest.txt
>>>
>>> I am following 325462-045US Jan 2013 sw dev manual and below are the
>>> counters
>>> which I cannot poke at via pmcstat:
>>>
>>> Core:
>>> "L2_RQSTS.DEMAND_DATA_RD_MISS"
>>> "L2_RQSTS.DEMAND_DATA_RD_HIT"
>>> "L2_RQSTS.ALL_DEMAND_DATA_RD"
>>> "L2_RQSTS.ALL_DEMAND_MISS"
>>> "L2_RQSTS.ALL_DEMAND_REFERENCES"
>>> "L2_RQSTS.MISS"
>>> "CYCLE_ACTIVITY.STALLS_L2_PENDING"
>>> "PAGE_WALKER_LOADS.DTLB_L1"
>>> "PAGE_WALKER_LOADS.ITLB_L1"
>>> "BACLEARS.ANY"
>>> "L2_LINES_OUT.DEMAND_CLEAN"
>>>
>>> Uncore:
>>> "UNC_CBO_XSNP_RESPONSE.INVAL_M"
>>> "UNC_CBO_CACHE_LOOKUP.ES"
>>>
>>> For all of them, I get error like this:
>>>
>>> # pmcstat -p L2_RQSTS.MISS ls
>>> pmcstat: ERROR: Cannot allocate process-mode pmc with specification
>>> "L2_RQSTS.MISS": Invalid argument
>>>
>>> Box does not panic or anything.
>>>
>>> I've tried to double check my changes without success.
>>> Is it possible that the documentation has some inconsistencies?
>>>
>>
>> It looks like IAF_F_FM is missing from most (all?) of the new event w/
>> umask entries you added that are specific to Haswell.  Can you try adding
>> these and see if it clears anything up?  A cursory look seemed to show most
>> of these failures are on event/umasks that are missing this flag.
>>
> Ah, good point. Let me try that and let you know.

Jim, thanks for spotting this. Missing counters are fixed now.

cheers,
Hiren
>
> Thanks,
> Hiren.
>> Thanks,
>>
>> -Jim