Hello FreeBSD-CURRENT and FreeBSD-X11 mailing list(s), I have a patch to add support for kernel mode setting on Intel Haswell/4th generation Core i(3/5/7) chips. The patch is: diff -u -r -N head/sys/dev/agp/agp_i810.c tree/sys/dev/agp/agp_i810.c --- head/sys/dev/agp/agp_i810.c 2013-11-11 16:18:23.000000000 -0500 +++ tree/sys/dev/agp/agp_i810.c 2013-11-11 17:09:33.000000000 -0500 _at__at_ -734,6 +734,41 _at__at_ .name = "IvyBridge server GT2 IG", .driver = &agp_i810_sb_driver }, + { + .devid = 0x04028086, + .name = "Haswell desktop GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x04128086, + .name = "Haswell desktop GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x04068086, + .name = "Haswell mobile GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x04168086, + .name = "Haswell mobile GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x040a8086, + .name = "Haswell server GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x041a8086, + .name = "Haswell server GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x0c168086, + .name = "Haswell SDV", + .driver = &agp_i810_sb_driver + }, { .devid = 0, } diff -u -r -N head/sys/dev/drm2/drm_pciids.h tree/sys/dev/drm2/drm_pciids.h --- head/sys/dev/drm2/drm_pciids.h 2013-11-11 16:17:33.000000000 -0500 +++ tree/sys/dev/drm2/drm_pciids.h 2013-11-11 17:09:37.000000000 -0500 _at__at_ -48,6 +48,42 _at__at_ {0x8086, 0x0162, CHIP_I9XX|CHIP_I915, "Intel IvyBridge"}, \ {0x8086, 0x0166, CHIP_I9XX|CHIP_I915, "Intel IvyBridge (M)"}, \ {0x8086, 0x016A, CHIP_I9XX|CHIP_I915, "Intel IvyBridge (S)"}, \ + {0x8086, 0x0402, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0412, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0422, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0406, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0416, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0426, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x040A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x041A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x042A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0C02, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0C12, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0C22, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0C06, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0C16, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0C26, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0C0A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0C1A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0C2A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0A02, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0A12, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0A22, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0A06, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0A16, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0A26, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0A0A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0A1A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0A2A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0D12, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0D22, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0D32, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \ + {0x8086, 0x0D16, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0D26, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0D36, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \ + {0x8086, 0x0D1A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0D2A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ + {0x8086, 0x0D3A, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \ {0x8086, 0x2562, CHIP_I8XX, "Intel i845G GMCH"}, \ {0x8086, 0x2572, CHIP_I8XX, "Intel i865G GMCH"}, \ {0x8086, 0x2582, CHIP_I9XX|CHIP_I915, "Intel i915G"}, \ diff -u -r -N head/sys/dev/drm2/i915/i915_drv.c tree/sys/dev/drm2/i915/i915_drv.c --- head/sys/dev/drm2/i915/i915_drv.c 2013-11-11 16:17:24.000000000 -0500 +++ tree/sys/dev/drm2/i915/i915_drv.c 2013-11-11 17:10:05.000000000 -0500 _at__at_ -173,6 +173,22 _at__at_ .has_llc = 1, }; +static const struct intel_device_info intel_haswell_d_info = { + .is_haswell = 1, .gen = 8, + .need_gfx_hws = 1, .has_hotplug = 1, + .has_bsd_ring = 1, + .has_blt_ring = 1, + .has_llc = 1, +}; + +static const struct intel_device_info intel_haswell_m_info = { + .is_haswell = 1, .gen = 8, .is_mobile = 1, + .need_gfx_hws = 1, .has_hotplug = 1, + .has_bsd_ring = 1, + .has_blt_ring = 1, + .has_llc = 1, +}; + #define INTEL_VGA_DEVICE(id, info_) { \ .device = id, \ .info = info_, \ _at__at_ -226,6 +242,42 _at__at_ INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ + INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ + INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ + INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ + INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ + INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ + INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ + INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ + INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ + INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ + INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ + INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ + INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ + INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ + INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ + INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ + INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ + INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ + INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ + INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ + INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ + INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ + INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ + INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ + INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ + INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ + INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ + INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ + INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ + INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ + INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ + INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ + INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ + INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ + INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ + INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ + INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ {0, 0} }; diff -u -r -N head/sys/dev/drm2/i915/i915_drv.h tree/sys/dev/drm2/i915/i915_drv.h --- head/sys/dev/drm2/i915/i915_drv.h 2013-11-11 16:17:24.000000000 -0500 +++ tree/sys/dev/drm2/i915/i915_drv.h 2013-11-11 17:10:05.000000000 -0500 _at__at_ -152,6 +152,7 _at__at_ u8 is_broadwater:1; u8 is_crestline:1; u8 is_ivybridge:1; + u8 is_haswell:1; u8 has_fbc:1; u8 has_pipe_cxsr:1; u8 has_hotplug:1; _at__at_ -1406,6 +1407,7 _at__at_ #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) +#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) /* XXXKIB LEGACY */ diff -u -r -N head/sys/dev/drm2/i915/i915_irq.c tree/sys/dev/drm2/i915/i915_irq.c --- head/sys/dev/drm2/i915/i915_irq.c 2013-11-11 16:17:26.000000000 -0500 +++ tree/sys/dev/drm2/i915/i915_irq.c 2013-11-11 17:10:05.000000000 -0500 _at__at_ -1875,6 +1875,14 _at__at_ dev->driver->irq_uninstall = ironlake_irq_uninstall; dev->driver->enable_vblank = ivybridge_enable_vblank; dev->driver->disable_vblank = ivybridge_disable_vblank; + } else if (IS_HASWELL(dev)) { + /* Share interrupts handling with IVB */ + dev->driver->irq_handler = ivybridge_irq_handler; + dev->driver->irq_preinstall = ironlake_irq_preinstall; + dev->driver->irq_postinstall = ivybridge_irq_postinstall; + dev->driver->irq_uninstall = ironlake_irq_uninstall; + dev->driver->enable_vblank = ivybridge_enable_vblank; + dev->driver->disable_vblank = ivybridge_disable_vblank; } else if (HAS_PCH_SPLIT(dev)) { dev->driver->irq_handler = ironlake_irq_handler; dev->driver->irq_preinstall = ironlake_irq_preinstall; Sorry if I sent a similar patch before. It didn't get accepted so I am sending one now. Enjoy. Thanks, NeelReceived on Mon Nov 11 2013 - 21:36:41 UTC
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