Hi, On 02/21/16 17:27, Larry Rosenman wrote: > On 2016-02-21 07:43, Hans Petter Selasky wrote: >> On 02/21/16 14:33, Dimitry Andric wrote: >>> If you ask me, something is just seriously broken in the way the xhci >>> driver works on Haswell or higher Intel CPUs. For example, on an >>> embedded Haswell box with USB3 ports: >> >> Hi, >> >> Nothing is seriously broken in the XHCI driver. Try to set: >> >> hw.usb.xhci.xhci_port_route=0 > > Does this DISABLE USB3? No, only the USB 2.x and 1.x part of the XHCI controller. >> >> Which will route all devices to the EHCI, in your /boot/loader.conf >> >> Does it make any difference? >> >> Refer to the following print: >>> xhci0: Port routing mask set to 0xffffffff >> >> The chipset you're using is special in that the binding of ports >> between XHCI and EHCI is not fixed. Maybe some combinations are simply >> not supported. >> > > Why is it "special"? It seems it's the norm for haswell and newer (in > my case Skylake). With special I mean, that the XHCI controller chipset has additional registers to switch the port routing between XHCI and EHCI for USB 2.0 and 1.0 devices. This was not part of the initial XHCI standard. I believe that is what the enumeration failures are about, that the USB 2.x/1.x lines are not properly routed to the XHCI in hardware. For the sake of the matter you can try to boot the Haswell chipset setting hw.usb.xhci.debug=16 in /boot/loader.conf, and send me the resulting log off-list, without using the hw.usb.xhci.xhci_port_route setting. And I'll see if there are any errors there which we can handle in software. --HPSReceived on Mon Feb 22 2016 - 06:03:27 UTC
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