WARNING: Bus mapping can be reliable only with direct hardware access enabled. 00:00.0 Class 0600: 1039:0646 (rev 01) Subsystem: 17c0:4000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- Reset- FastB2B- 00: 39 10 01 00 07 00 00 00 00 00 04 06 00 63 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 44 a0 a0 00 20 20: 10 ec 10 ec 00 f0 f0 f7 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0c 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ## 00.01:0 is a bridge from 00 to 01-01 00:02.0 Class 0601: 1039:0008 (rev 14) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset+ 16bInt+ PostWrite+ 16-bit legacy interface ports at 0001 00: 4c 10 55 ac 07 00 10 02 01 00 07 06 04 a8 82 00 10: 00 00 00 20 a0 00 00 02 02 03 03 b0 00 00 40 20 20: 00 f0 7f 20 00 00 80 20 00 f0 bf 20 00 40 00 00 30: fc 40 00 00 00 44 00 00 fc 44 00 00 0b 01 c0 05 40: c0 17 02 32 01 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 61 b0 44 08 00 00 00 00 00 00 00 00 22 10 00 01 90: c0 02 64 60 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 12 fe 00 00 c0 00 08 00 00 00 1f 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ## 00.09:0 is a bridge from 02 to 03-03 !!! Bridge points to invalid primary bus. 00:09.1 Class 0607: 104c:ac55 (rev 01) Subsystem: 17c0:3202 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- Reset+ 16bInt+ PostWrite+ 16-bit legacy interface ports at 0001 00: 4c 10 55 ac 07 00 10 02 01 00 07 06 04 a8 82 00 10: 00 10 00 20 a0 00 00 02 02 04 04 b0 00 00 c0 20 20: 00 f0 ff 20 00 00 00 21 00 f0 3f 21 00 48 00 00 30: fc 48 00 00 00 4c 00 00 fc 4c 00 00 0b 02 c0 05 40: c0 17 02 32 01 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 61 b0 44 08 00 00 00 00 00 00 00 00 22 10 00 01 90: c0 02 64 60 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 12 fe 00 00 c0 00 08 00 00 00 1f 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ## 00.09:1 is a bridge from 02 to 04-04 !!! Bridge points to invalid primary bus. 01:00.0 Class 0300: 1002:4c66 (rev 02) Subsystem: 17c0:2058 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B+ Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR-