Index: miidevs
===================================================================
RCS file: /home/ncvs/src/sys/dev/mii/miidevs,v
retrieving revision 1.41
diff -u -r1.41 miidevs
--- miidevs	21 Feb 2007 18:17:44 -0000	1.41
+++ miidevs	13 Mar 2007 00:42:49 -0000
@@ -67,6 +67,7 @@
 oui TDK				0x00c039	TDK
 oui TI				0x080028	Texas Instruments
 oui XAQTI			0x00e0ae	XaQti Corp.
+oui VITESSE			0x0001c1	Vitesse Semiconductor
 oui MARVELL			0x005043	Marvell Semiconductor
 oui xxMARVELL			0x000ac2	Marvell Semiconductor
 
@@ -135,6 +136,7 @@
 
 /* Cicada Semiconductor PHYs (now owned by Vitesse?) */
 model CICADA CS8201		0x0001 Cicada CS8201 10/100/1000TX PHY
+model VITESSE VSC8601		0x0002 VSC8601 10/100/1000TX PHY
 model CICADA CS8201A		0x0020 Cicada CS8201 10/100/1000TX PHY
 model CICADA CS8201B		0x0021 Cicada CS8201 10/100/1000TX PHY
 
Index: ciphy.c
===================================================================
RCS file: /home/ncvs/src/sys/dev/mii/ciphy.c,v
retrieving revision 1.8
diff -u -r1.8 ciphy.c
--- ciphy.c	2 Dec 2006 19:36:25 -0000	1.8
+++ ciphy.c	13 Mar 2007 00:42:49 -0000
@@ -91,6 +91,7 @@
 	MII_PHY_DESC(CICADA, CS8201),
 	MII_PHY_DESC(CICADA, CS8201A),
 	MII_PHY_DESC(CICADA, CS8201B),
+	MII_PHY_DESC(VITESSE, VSC8601),
 	MII_PHY_END
 };
 
@@ -339,7 +340,24 @@
 static void
 ciphy_reset(struct mii_softc *sc)
 {
+	struct mii_data *mii;
+	uint16_t val;
 
+	mii = sc->mii_pdata;
+	if (strcmp(mii->mii_ifp->if_dname, "nfe") == 0) {
+		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		val = PHY_READ(sc, CIPHY_MII_ECTL1);
+		val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
+		val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
+		PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
+		/* From Linux. */
+		val = PHY_READ(sc, CIPHY_MII_AUXCSR);
+		val |= CIPHY_AUXCSR_MDPPS;
+		PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
+		val = PHY_READ(sc, CIPHY_MII_10BTCSR);
+		val |= CIPHY_10BTCSR_ECHO;
+		PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
+	}
 	mii_phy_reset(sc);
 	DELAY(1000);
 }