Re: data corruption with current (maybe sis chipset related?)

Heiko Schaefer wrote:
> > Be that as it may, it was still he that suggested those options and
> > claims that he knows more. On my machine at work, a 1.8GHz P4, those
> > options give me a useable stable machine and without it I get signal
> > 10 and 11's left,right and center. That machine is building a snap
> > every night and has an uptime of 37 days because that is when I last
> > updated it.
> 
> the thread i found in -current archives suggested that these flags work
> around an amd-specific issue. now you say that a p4-based machine also
> needs them to run stable.

The problem appears on any processor that supports 4M pages;
that includes both Intel and AMD processors.  Whether or not
you personally see it is based on the memory usage patterns
that are required to trigger it.


> i am wondering more and more: why are these options not in GENERIC ?!?
> ...if someone knows what he's doing he can always throw them out again.
> 
> (just like back in the day, dma was not enabled by default...)

The were in the last developer preview.  There were specific
hacks for the P4, which would not have helped the AMD K6 (it
may be that other processors also have the problem, too; I
have only regressed it personally on P3's, P4's, and the AMD
K6).  They were removed after the autotuning changes by Matt
Dillon and the memory allocator changes by Jeff Robertson went
in.  Both changes added preterbations to the memory usage patterns
which, in my opinion, would add steep stair functions into where
you would see the problem occur, and tend to mask it on a large
variety of systems (but not all of them, so it's a land mine
waiting for the unexpecting person with the right hardware and
software combinations).

-- Terry