RE: STI, HLT in acpi_cpu_idle_c1

From: Matthew Dillon [mailto:dillon_at_apollo.backplane.com]
 ...
OK, i understand.

> 
>     So, if the emulator is not coming out of the HLT it's a 
> bug in the 
>     emulator.  The STI; HLT sequence is correct.

The emulator is doing the right thing. It breaks the 
processors out, and shows all the registers etc.
Its transparent, done via jtag (American Arium). In the 
lockup case i have, 3 processors are executing HLT, and 
EFLAGS bit 9 is clear. Thus I was wondering, it doesn't 
seem obvious as to where in the pipeline the STI will take 
affect. Is it at the end of the HLT instruction? Is this 'end'
when an interrupt occurs? The manual just says "after
the next instruction". Does that mean the instruction
following needs to start? Does the halt instruction
'end' when the processor goes to sleep, or when the
processor wakes up? What should I expect to see in
bit 9 of eflags when i'm executing HLT?

I can't otherwise find how my system is behaving.
The processors will service an NMI in this mode,
as i would expect, but will not service any normal
interrupts (serial, lan, hardclock). The sole
'awake' processor doesn't have any physical interrupts
routed to it, and the ones that do have the physical
interrupts have interrupts disabled.

I added a hack into ddb so that I could NMI in
in this case without hanging, and it finds that the IPI 
it sends to the other processors doesn't get answered: they
don't stop. So I have reverted to the hardware ICE
in order to find what is going on.

--don