RE: STI, HLT in acpi_cpu_idle_c1

From: Gerrit Nagelhout <gnagelhout_at_sandvine.com>
Date: Thu, 24 Jun 2004 10:36:04 -0400
Here's some information about another slightly different 
lockup.  CPU0 is blocked in smp_targeted_tlb_shootdown (vector 0xf5).
CPU2 & 3 are in acpi_cpu_c1.  CPU1 (again) is in acpi_cpu_c1,
but it has an interrupt pending.  In this case, the pending
interrupt is bit 27.  224 + 27 = 251 = IPI_HARDCLOCK.
How can I figure out how CPU1 got stuck in this state?  As
far as I can tell, there is either a h/w problem, or CPU1
has gone to sleep after starting to handle an interrupt.
Thanks,

Gerrit

P0>dumpAllLocalApic
CPU 0
ID:    0x6000000 
TPR:   0x0 
PPR:   0x0 
icr_lo:0xf5 
APR:   0x0 
ISR0:  0x0 
ISR1:  0x0 
ISR2:  0x0 
ISR3:  0x0 
ISR4:  0x0 
ISR5:  0x0 
ISR6:  0x0 
ISR7:  0x0 
IRR0:  0x0 
IRR1:  0x0 
IRR2:  0x0 
IRR3:  0x0 
IRR4:  0x0 
IRR5:  0x0 
IRR6:  0x0 
IRR7:  0x18000000 
TMR0:  0x0 
TMR1:  0x0 
TMR2:  0x0 
TMR3:  0x0 
TMR4:  0x0 
TMR5:  0x0 
TMR6:  0x0 
TMR7:  0x0 
CPU 1
ID:    0x7000000 
TPR:   0x0 
PPR:   0xf0 
icr_lo:0xf3 
APR:   0x0 
ISR0:  0x0 
ISR1:  0x0 
ISR2:  0x0 
ISR3:  0x0 
ISR4:  0x0 
ISR5:  0x0 
ISR6:  0x0 
ISR7:  0x8000000 
IRR0:  0x0 
IRR1:  0x0 
IRR2:  0x0 
IRR3:  0x0 
IRR4:  0x0 
IRR5:  0x0 
IRR6:  0x0 
IRR7:  0x18200000 
TMR0:  0x0 
TMR1:  0x0 
TMR2:  0x0 
TMR3:  0x0 
TMR4:  0x0 
TMR5:  0x0 
TMR6:  0x0 
TMR7:  0x0 
CPU 2
ID:    0x0 
TPR:   0x0 
PPR:   0x0 
icr_lo:0xfb 
APR:   0x0 
ISR0:  0x0 
ISR1:  0x0 
ISR2:  0x0 
ISR3:  0x0 
ISR4:  0x0 
ISR5:  0x0 
ISR6:  0x0 
ISR7:  0x0 
IRR0:  0x0 
IRR1:  0x1000000 
IRR2:  0x0 
IRR3:  0x0 
IRR4:  0x20000 
IRR5:  0x0 
IRR6:  0x0 
IRR7:  0x0 
TMR0:  0x0 
TMR1:  0x0 
TMR2:  0x1000 
TMR3:  0x0 
TMR4:  0x20000 
TMR5:  0x0 
TMR6:  0x0 
TMR7:  0x0 
CPU 3
ID:    0x1000000 
TPR:   0x0 
PPR:   0x0 
icr_lo:0xf3 
APR:   0x0 
ISR0:  0x0 
ISR1:  0x0 
ISR2:  0x0 
ISR3:  0x0 
ISR4:  0x0 
ISR5:  0x0 
ISR6:  0x0 
ISR7:  0x0 
IRR0:  0x0 
IRR1:  0x0 
IRR2:  0x0 
IRR3:  0x0 
IRR4:  0x0 
IRR5:  0x0 
IRR6:  0x0 
IRR7:  0x0 
TMR0:  0x0 
TMR1:  0x0 
TMR2:  0x0 
TMR3:  0x0 
TMR4:  0x0 
TMR5:  0x0 
TMR6:  0x0 
TMR7:  0x0 
P3>
P3>
Received on Thu Jun 24 2004 - 12:36:33 UTC

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