On Wed, 2005-Apr-27 19:27:20 -0700, /dev/null wrote: >In my case I think it was just "sync" issues between the CPU cache and >the RAM. Although it could have been just that this processor drove >the RAM stick hard enough to make it fail. No matter, the stick of RAM is >working flawlessly in a different box. :) Modern hardware is pushed very close to the limits. Maybe the RAM has some pattern sensitivity that just happens to be hit by buildkernel or buildworld. Maybe a combination of marginal bypass capacitors, marginal memory bus drivers means that the logic transition is a few picoseconds longer than desirable if a large number of bits change state simultaneously so that the transition isn't seen by the marginal receiver. -- Peter JeremyReceived on Thu Apr 28 2005 - 06:29:44 UTC
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