> On Wed, 2005-Apr-27 19:27:20 -0700, /dev/null wrote: >>In my case I think it was just "sync" issues between the CPU cache and >>the RAM. Although it could have been just that this processor drove >>the RAM stick hard enough to make it fail. No matter, the stick of RAM is >>working flawlessly in a different box. :) > > Modern hardware is pushed very close to the limits. Maybe the RAM has > some pattern sensitivity that just happens to be hit by buildkernel or > buildworld. Maybe a combination of marginal bypass capacitors, > marginal memory bus drivers means that the logic transition is a few > picoseconds longer than desirable if a large number of bits change > state simultaneously so that the transition isn't seen by the marginal > receiver. > Good point(s). I sure wish I could just use 1 giant can capacitor that simply fills as required and releases as necessary. It would be so much simpler. On a sad note, after a long period of usage it still fails. So it seems that the new CPU is the culprit (CPU's cache?). Anyway, I might disable the CPU's cache in the bios settings and see what happens, while I wait for another CPU. Best wishes, Chris > -- > Peter Jeremy > //////////////////////////////////////////////////// If only Western Electric had found a way to offer binary licenses for the UNIX system back in 1974, the UNIX system would be running on all PC's today rather than DOS/Windows. ////////////////////////////////////////////////////Received on Thu Apr 28 2005 - 17:44:49 UTC
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