On Sun, 2006-Jul-30 11:07:31 +0200, Michal Mertl wrote: >Paul Allen wrote: >> Which FreeBSD tier-I 64b arch do you have in mind... > >I was referring to what Peter Jeremy said earlier in this thread: > >> RISC architectures usually only have TAS lock primitives (because "inc >> mem" doesn't exist) and so require a spinlock to perform an atomic >> update. This was based on an examination of /usr/src/sys/*/include/atomic.h. It looks like I was overly quick because the RISC architectures are using compare-and-swap, rather than test-and-set primitives - sorry about the error. The details are: - Alpha (RIP) used a loop around a locked conditional store - amd64 appears to support RMW - arm doesn't support 64-bit atomic operations - i386 doesn't support 64-bit atomic operations (but could implement them using cmpxchg8b in a loop) - ia64 uses cmpxchg in a loop - ppc doesn't support 64-bit atomic operations - sparc64 uses cas in a loop. Whilst true spinlocks are not needed, amd64 is the only architecture FreeBSD supports that does not require some sort of loop to perform a 64-bit atomic operation. -- Peter Jeremy
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