Re: TSC Timecounter and multi-core/SMP

Poul-Henning Kamp wrote:
> In message <47FE7E0C.4070801_at_FreeBSD.org>, Maxim Sobolev writes:
>> Kris Kennaway wrote:
>>> gnn_at_freebsd.org wrote:
>>>> Howdy,
>>>>
>>>> Is the TSC timecounter synchronized across multiple cores and/or
>>>> processors?  A quick search seems to indicate it's not but I'd like to
>>>> find a definitive reference on the TSC.
>>> Modern Intel systems tend to be synchronized, in my experience.
>> I really doubt they are. As far as I know newest milti-core chips can 
>> modulate frequency of even suspend individual cores independently of 
>> each other, which would make such synchronization difficult to maintain 
>> if the power management is on.
> 
> P4 (and I think most newer chips) have a TSC that runs independent
> of the cpu clock frequency, and supposedly, always at constant rate.

It can still be affected by the throttling. The p4tcc driver can for 
example can throttle separate processors independently.

Quick google search brings this up:

http://lkml.org/lkml/2005/11/4/173

-Maxim