Re: One-shot-oriented event timers management

Gary Jennejohn wrote:
> On Mon, 30 Aug 2010 13:07:38 +0300
> Alexander Motin <mav_at_FreeBSD.org> wrote:
>> Yes, as I have said, at this moment empty ticks skipped only while CPU
>> is in C2/C3 states. In C1 state there is no way to handle lost events on
>> wake up. While it may be not very dangerous, it is not very good.
>>
> Too bad.  I'd say that systems which are limited to C1 don't benefit
> much (or not at all) from your changes.

I've solved it! :)

I've recalled that most of our interrupts are working in interrupt
threads. It means that it may be not so important to disable interrupts
completely, but only delay their threads execution by putting cpu_idle()
inside critical section and releasing it only after all missed events
handled. Sure, this approach will not help FILTER interrupt handlers,
executed inside hardware interrupt context, but we have very few of them
and they are usually very simple and I hope not very depend on system
time precision.

Also this new approach allows simple interrupts (like TLB invalidation
IPIs) to execute before processing lost events. It should reduce
performance penalty. To limit penalty even more, I have added counting
of cpu_idle() calls per HZ tick. It allows to bypass timer stuff if CPU
wakes up too often. It should help handle high interrupt rates without
high overhead.

Also I have added set of checks, blocking ACPI C3 state usage when
C3-variant APIC timer is used and reduced priority of such timer. It
makes use of C3 state usage safe enough and often allows AMD CPUs to not
disable C1E state as it was done before.

New patch is here: http://people.freebsd.org/~mav/timers_oneshot5.patch

-- 
Alexander Motin